EDA Week in Review - By Ann Steffora, EDAtoolsCafe/EDAVision Managing Editor

March 4-8, 2002 -- By far, the biggest news in the EDA industry, on the business side, was the board at IKOS acknowledging that Mentor Graphic’s merger agreement offer was financially more beneficial, and that it would like to move forward in that direction, thereby requesting to Synopsys that it terminate the original agreement between the companies.

According to a Synopsys statement, under the existing Synopsys-IKOS merger agreement, the delivery of the notice from IKOS means that, subject to certain conditions, IKOS may be able to terminate the Synopsys - IKOS merger agreement after 6 p.m. PST on Monday, March 11, 2002. Synopsys said it is reviewing the IKOS notice, and has until 6 p.m. PST on Monday, March 11, 2002 to respond to IKOS' notice.

IKOS shareholders should be happy about this development since they could gain a better price for their stock by going with Mentor, and from a business perspective, the IKOS tools fit better into Mentor’s product portfolio than Synopsys’.

Click here for the full announcements

In other news, the VSI Alliance (VSIA) said it is launching an Embedded Software Reuse Initiatives to help solve the increasing embedded software design productivity gap in SoCs. Robert Payne, US CTO & VP/GM of System ASIC Technology, Philips Semiconductors, will discuss the current embedded software reuse and platform-based design issues for SoCs at the VSIA General Meeting at the Embedded Systems Conference San Francisco, March 14, 2002, from 4:30 - 8:00 p.m. at the Moscone Convention Center, San Francisco, Room 270-276.

The VSIA has also formed a new Hardware-dependent Software (HdS) Development Working Group (DWG), Platform-Based Design (PBD) Study Group, and during the meeting at the Embedded Systems Conference, VSIA will reveal its plans to address these embedded software issues by new co-chairs Michael Kaskowitz, VP/GM Embedded Systems Division of Mentor Graphics, and Bob Altizer, VSIA individual member, formerly with Motorola.

Also at this meeting, VSIA’s work in the areas of Virtual Component Transfer (VCT) and Signal Integrity (SI) will be presented by William McVay, VSIA VCT DWG chairman and IP coordinator, Alcatel; and Raminderpal Singh, VSIA Analog-Mixed Signal (AMS) SI Subgroup chairman, and senior engineer, RF/AMS Design Kits Development, International Business Machines Corp. The event is open to all engineers, developers, and project managers of the EDA and embedded systems communities.

Click here for the full announcements:

http://biz.yahoo.com/bw/020305/52238_1.html

http://biz.yahoo.com/bw/020305/52233_1.html

Product News

“With the 2.3 release, IC Wizard leverages its foundation of physical planning capabilities to include timing analysis, constraint budgeting and allocation, and model generation,” said Wolfgang Helfricht, product marketing director at Monterey, in the company’s announcement.

Click here for the full announcement.

In addition to business news, Mentor Graphics and Synopsys shared product news this week with new tools and activities for programmable logic devices.

Mentor announced comprehensive design tool support for the new Virtex-II Pro FPGA family from Xilinx, Inc. Extracting maximum performance from the Virtex-II Pro family for applications, such as high-speed data communications systems, requires an end-to-end design and verification solution comprising tools for creation through synthesis, Mentor said. In order to accomplish this, Xilinx and Mentor Graphics have teamed to ensure that tool development occurs in lockstep with new architecture announcements.

“Combining microprocessors with multi-gigabit serial transceivers on a single device introduces a level of design complexity that forces closer relationships with the EDA community,” said Rich Sevcik, senior vice president, FPGA Products at Xilinx, in the Mentor announcement.

“In tandem with our introduction of the Virtex-II Pro family, Mentor Graphics delivers a state-of-art synthesis tool, Precision Synthesis, that is uniquely tailored to address the timing optimization challenges of cutting-edge FPGA design,” Sevcik added.

The new Precision Synthesis environment, is a synthesis platform that maximizes the performance of both existing programmable logic devices (PLD) and next-generation, multi-million gate field programmable system-on-chip (FPSoC) devices, Mentor said.

Powered in part by the company’s Exemplar technology, Precision Synthesis is at the heart of Mentor’s company-wide initiative to provide a comprehensive tool suite, from design creation through verification and system integration, and intellectual property cores, for the broad spectrum of FPGA designs.

The new tool delivers a scalable synthesis platform available for designers implementing a full-range of programmable logic devices, including the Stratix and Excalibur architectures from Altera and the new Virtex-II Platform FPGAs by Xilinx.

The tool features an intuitive graphical user interface, a new suite of optimization algorithms (A.S.E. optimization) and a state-of-the-art-timing engine (PreciseTime) that delivers the industry's most accurate timing analysis.

Click here for the full announcements:

http://www10.dacafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=21302

http://www10.dacafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=21023

From the Synopsys camp comes version 3.7 of its two FPGA synthesis solutions--FPGA Compiler II and FPGA Express. The new releases offers enhancements aimed to make designing FPGAs easier by increasing both language and scripting flexibility and adding support for the latest programmable logic devices from Altera Corp. and Xilinx. Version 3.7 is also the final release of FPGA Express, which was previously available only in Altera and Xilinx OEM kits, Synopsys reported. FPGA Compiler II will supercede FPGA Express. When upgrading to FPGA Compiler II, FPGA Express customers benefit from advanced functionality for high-end design, product updates and world-class support, Synopsys also said.

Version 3.7 of FPGA Compiler II and FPGA Express brings designers enhanced Verilog support and an improved command shell. In addition, this version of FPGA Compiler II extends its unique capability of handling elements from the Synopsys DesignWare library to further aid designers who use FPGAs as prototypes for ASICs. With a new User’s Guide to complement the existing Design Wizard, FPGA Compiler II offers a quick start for both graphic user interface and scripting-oriented FPGA designers, and includes specialized algorithms for the Altera Stratix and Xilinx VirtexII Pro families of devices.

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Sequence Design announced the addition of IP power modeling to its NanoCool initiative for 100 nanometer low-power/low-voltage design. Sequence said the NanoCool flow would leverage its expertise in RTL power, concurrent optimization, and extraction to partner with industry leaders to address the unique needs of designs at 100 nanometers and below. Initial partners in the initiative include Silicon Metrics and Virtual Silicon.

IP modeling will be available in April 2002 as part of the standard feature set of PowerTheater Analyst for existing customers with current maintenance contracts, as well as new customers starting at $80,000 for a one-year time-based license in Europe and the United States, Sequence said.

Click here for the full announcement:

http://www.sequencedesign.com/3_news/pr_archives/030502.html

http://www.sequencedesign.com/3_news/pr_archives/022502.html

STMicroelectronics was the focus of three partnerships announced this week by Synopsys, Model Technology and Celestry.

Synopsys Inc. announced a two-year partnership with STMicroelectronics to focus on creating new methodologies and technologies to reduce manufacturing test development cost and effort while simultaneously improving test quality, the companies said. This new alliance is to develop and deploy advanced manufacturing test solutions innovated by Synopsys and STMicroelectronics that solve test challenges at reduced costs, and provide turnaround time and time to market advantages for complex systems-on-chip (SoC) devices. This new alliance also expands on the accomplishments of an earlier ST/Synopsys test partnership -- enabling design-for-test (DFT) closure for SoC design flows -- by adding two major objectives: First, the alliance will aim to optimize ST's design-to-manufacturing test flows to greatly improve turnaround time and time to market. Second, it will strive to enable ST to dramatically reduce its manufacturing test costs. To accomplish these objectives, ST brings its experience as an integrated device manufacturer with a comprehensive view of SoC design and manufacturing, and Synopsys brings its innovations in DFT technology and expertise in unifying design and manufacturing test.

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Model Technology, a Mentor Graphics company, announced that the ModelSim hardware description language (HDL) simulation tool has achieved Verilog sign-off status with STMicroelectronics and will be used to verify next-generation 0.18 and 0.13-micron designs for products within the global telecommunications sector.

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And Celestry Design Technologies, provider of physical analysis software and services, said STMicroelectronics has selected Celestry's Hot-Carrier Injection (HCI) analysis products to increase the performance of ST's high-end designs.

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Centillium Communications said Artisan Component's industry-standard library products were used in its Entropia and CopperFlite families of products. Centillium's design challenge was to develop high-density products utilizing TSMC's 0.18-micron low-voltage process. Artisan provided its TSMC process-optimized memory generators and SAGE-X Standard Cell Library. With Artisan's libraries integrated into Centillium's Entropia and CopperFlite products, Centillium said it could provide innovative products optimized for speed and density to its customers.

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Cadence Design Systems announced a new NC-Sim Plus package that provides an integrated front-end logic design solution. NC-Sim Plus includes the Cadence NC-Sim mixed language simulator, TestBuilder open-source testbench development tool, Verification Cockpit functional verification tool, and the BuildGates synthesis tool.

“In this era of multi-million gate ASICs, reusable IP, and SoC designs, verification has become the major bottleneck in getting designs released,” said Rahul Razdan, corporate vice president and general manager of Systems and Functional Verification at Cadence, in the company’s announcement. “It is a real challenge for engineers to know when a design has been verified and meets specified implementation criteria. Our unique solution combines the tools required to provide reliable answers to today’s verification-through-implementation challenges.”

Cadence said NC-Sim Plus directly addresses the key challenge that verification engineers face: the lack of a reliable means to confirm that their design has been fully verified. Without this information, designers are often caught in a cycle of design respins that are costly and time-consuming. NC-Sim Plus brings together the tools that give engineers the confidence that their designs have been fully verified.

At the center of this new product bundle is NC-Sim, the mixed-language simulator. It was designed to handle the most complex ASIC, SoC, and FPGA designs. The open-source TestBuilder testbench development tool provides the first step in creating a transaction-based verification environment. It is based on the familiar C++ language and includes a set of C++ class libraries with the transaction models and functions designers need.

Click here for the full announcement.

Also from Cadence comes an upgrade to its Signal Processing Worksystem (SPW), a system-level, hierarchical block diagram design solution wit